1. Field of the Invention
The present invention relates to an emitter-coupled logic (ECL) type semiconductor memory device manufactured by a master slice method. More particularly, the present invention relates to an ECL type a semiconductor memory device with an optimal number of word line driver stages.
2. Description of the Related Art
ECL memory devices using bipolar transistors have been made with increasingly larger capacities in recent years. This has been accompanied by an increase of the load of the word lines. To deal with this increased load, it is effective to form the word line drivers as a two-stage emitter-follower (EF) construction or a Darlington connection to raise the drive capacity. This enables a high speed operation and low power consumption.
ECL memory devices come in two types, "10K" and "100k". The input and output levels of these are almost the same, but their temperature characteristics are different. That is, the 10K type device has a temperature coefficient the same as that of a forward voltage V.sub.F of a diode in the circuit, while the 100K type device internally compensates for the temperature characteristics to achieve the temperature coefficient of zero. Which type of device to be used depends on the specific application of the device.
Another difference between the two types of ECL memory devices lies in the voltage of the power source. An ECL memory device operates between an earth potential (V.sub.CC) and a negative power source (V.sub.EE). The negative power source voltage V.sub.EE is usually -5.2 V for a 10K type device and -4.5 V for a 100K type device. That is, a 10K type device can operate with a power source voltage of 0.7 V lower than the 100K type device, i.e., the power source margin of the 10K type device is larger than the 100K type device. Those two types of devices have the same latent power source margin.
The only difference in the conventional circuit constructions of the 100K and 10K type devices is that the 100K type device provides a diode in the output buffer gate compensating for the temperature characteristic of the output voltage and another diode for adjusting the threshold level of input buffer gate due to receiving constant voltage swings. Therefore, the 100K and 10K type devices can be manufactured by substantially the same wafer process. To manufacture the 100K type device the wiring process is changed to add the diodes. The method for producing devices of this type is called a master slice method.
When the word line driver is constructed in two stages, the voltage of the word lines becomes low and the voltage levels supplied to word lines and bit lines become low corresponding to the voltage drop of the word lines. This narrows the power source margin in the 100K type device, which must be operated in a voltage region around -4.5 V. Actually most memory devices which have two-stage word drivers cannot operate at -4.5 V.
This means that the word line driver in a 100K type device must be constructed in one stage. When using the master slice method and conventional circuit technology, therefore, even the 10K type device must have the word driver constructed in one stage. This, however, means a high-speed operation cannot be obtained with a 10K type device despite its sufficient power source margin.